Implementation of analog processors and neural systems require compact storage of a large number of analog parameters (voltage or current). In this regard, floating-gate (FG) transistors are attractive for implementing high-density, non-volatile current memories. Two types of FG current-memories have been reported in literature and are summarized below. With reference to FIG. 1A, the first variant of the FG current memory consists of a pre-compensation stage formed by a FG transistor P1 and an output transistor P2, which forms the current memory cell. A and B are the floating-gate nodes where the charge is stored. Because the nodes are completely insulated by high quality silicon-dioxide, any charge trapped on it is retained for a long period of time (8 bits retention accuracy for less than 8 years). If QA and QB denote the charge stored on nodes A and B respectively, then the output current Iout can be expressed as
                                          I            out                    ≈                                    I              ref                        ⁢                          exp              ⁡                              (                                  κ                  ⁢                                                                                    Q                        B                                            -                                              Q                        A                                                                                                            C                        T                                            ⁢                                              U                        T                                                                                            )                                                    ,                            (        1        )            where κ is the gate-efficiency factor, CT is the total capacitance seen at nodes A and B, and UT=kT/q is the thermal voltage which is directly proportional to temperature T. Equation (1) illustrates that Iout exhibits an exponential dependence with respect to temperature.
With reference to FIG. 1B, the second variant of the FG current memory overcomes this problem by using a modified version of a standard PTAT. Note that instead of using different sizes of pMOS transistors in the current mirror, the circuit uses a floating-gate voltage element formed by the capacitor C. If the charge on C is denoted by Q and if all the transistors are biased in weak-inversion, then the output current is given byIout≈κQ/CTR,  (2)where CT is again the total capacitance seen at node D. Provided the resistance R is compensated for temperature, the output current will also be compensated for temperature. However, compared to the current memory in FIG. 1A, the memory shown in FIG. 1B requires a large resistance (>100MΩ) for generating sub-threshold currents, which prohibits its application for high-density arrays. Also, the quality of temperature compensation deteriorates at ultra-low currents or when active resistances are used for emulating a larger R. Hence, an alternative approach is proposed for implementing temperature-compensated floating-gate current memories that can achieve high integration density.
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